AES_CTRL_GCM=AES_CTRL_GCM_NOP, AES_CTRL_XTS=AES_CTRL_XTS_NOP, AES_CTRL_CTR_WIDTH=AES_CTRL_CTR_WIDTH_32
AES Control
| AES_CTRL_OUTPUT_READY | Output Ready Status |
| AES_CTRL_INPUT_READY | Input Ready Status |
| AES_CTRL_DIRECTION | Encryption/Decryption Selection |
| AES_CTRL_KEY_SIZE | Key Size 1 (AES_CTRL_KEY_SIZE_128): Key is 128 bits 2 (AES_CTRL_KEY_SIZE_192): Key is 192 bits 3 (AES_CTRL_KEY_SIZE_256): Key is 256 bits |
| AES_CTRL_MODE | ECB/CBC Mode |
| AES_CTRL_CTR | Counter Mode |
| AES_CTRL_CTR_WIDTH | AES-CTR Mode Counter Width 0 (AES_CTRL_CTR_WIDTH_32): Counter is 32 bits 1 (AES_CTRL_CTR_WIDTH_64): Counter is 64 bits 2 (AES_CTRL_CTR_WIDTH_96): Counter is 96 bits 3 (AES_CTRL_CTR_WIDTH_128): Counter is 128 bits |
| AES_CTRL_ICM | AES Integer Counter Mode (ICM) Enable |
| AES_CTRL_CFB | Full block AES cipher feedback mode (CFB128) Enable |
| AES_CTRL_XTS | AES-XTS Operation Enabled 0 (AES_CTRL_XTS_NOP): No operation 1 (AES_CTRL_XTS_TWEAKJL): Previous/intermediate tweak value and j loaded (value is loaded via IV, j is loaded via the AAD length register) 2 (AES_CTRL_XTS_K2IJL): Key2, n and j are loaded (n is loaded via IV, j is loaded via the AAD length register) 3 (AES_CTRL_XTS_K2ILJ0): Key2 and n are loaded; j=0 (n is loaded via IV) |
| AES_CTRL_F8 | AES f8 Mode Enable |
| AES_CTRL_F9 | AES f9 Mode Enable |
| AES_CTRL_CBCMAC | AES-CBC MAC Enable |
| AES_CTRL_GCM | AES-GCM Mode Enable 0 (AES_CTRL_GCM_NOP): No operation 1 (AES_CTRL_GCM_HLY0ZERO): GHASH with H loaded and Y0-encrypted forced to zero 2 (AES_CTRL_GCM_HLY0CALC): GHASH with H loaded and Y0-encrypted calculated internally 3 (AES_CTRL_GCM_HY0CALC): Autonomous GHASH (both H and Y0-encrypted calculated internally) |
| AES_CTRL_CCM | AES-CCM Mode Enable |
| AES_CTRL_CCM_L | L Value 1 (AES_CTRL_CCM_L_2): width = 2 3 (AES_CTRL_CCM_L_4): width = 4 7 (AES_CTRL_CCM_L_8): width = 8 |
| AES_CTRL_CCM_M | Counter with CBC-MAC (CCM) |
| AES_CTRL_SAVE_CONTEXT | TAG or Result IV Save |
| AES_CTRL_SVCTXTRDY | AES TAG/IV Block(s) Ready |
| AES_CTRL_CTXTRDY | Context Data Registers Ready |